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7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 1 white electronic designs corporation ? (508) 366-5151 technical specifications ata 20 series flash cards 7p008ata2003c25 8mb 7p016ata2003c25 16mb 7p032ata2003c25 32mb 7p048ata2003c25 48mb 7p064ata2003c25 64mb 7P080ATA2003C25 80mb 7p096ata2003c25 96mb 7p112ata2003c25 112mb 7p128ata2003c25 128mb 7p160ata2003c25 160mb description models 7p008ata20, 7p016ata20, 7p032ata20, 7p048ata20, 7p064ata20, 7p080ata20, 7p096ata20, 7p112ata20, 7p128ata20 and 7p160ata20 are flash ata cards. they comply with the pc card ata standard and are suitable for usage as a data storage memory medium for pcs or other electronic equipment. these cards are built with hitachi 64 mb flash memory devices hn29w6411. the cards are suitable for the isa (industry standard architecture) bus interface standard. the read/write unit is 1 sector (512 bytes) sequential access. features ? pc card ata standard specification ? 68 pin two piece connector and type i (3.3 mm) or type ii (5 mm) stainless steel housing ? 3.3 v/5 v single power supply operation ? isa standard and read/write unit is 512 bytes (sector) sequential access ? sector read/write transfer rate: 8mb/sec burst ? high reliability based on internal ecc (error correcting code) function ? maximum card density is 160mb ? cards are built with hitachi 64 mb flash memory devices (hn29w6411a) ? 3 variations of mode access ? memory card mode ? i/o card mode ? true-ide mode ? internal self-diagnostic program operates at v cc power on ? high reliability based on wear leveling function ? data write endurance is 300,000 cycles (with approximately 500 kb dos file) ? data reliability is 1 error in 10 14 bits read. ? industrial temperature range version: -40 c to +85 c ? auto sleep function
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 2 white electronic designs corporation ? (508) 366-5151 card line up card type card density capacity (3) total sectors/ card (2) sectors / track number of heads number of cylinder 7p008ata2003c25 8mb 8,060,928 byte 15,744 32 2 246 7p016ata2003c25 16mb 16,121,856 byte 31,488 32 4 246 7p032ata2003c25 32mb 32,243,712 byte 62,976 32 4 492 7p048ata2003c25 48mb 48,365,568 byte 94,464 32 4 738 7p064ata2003c25 64mb 64,487,424 byte 125,952 32 4 984 7P080ATA2003C25 80mb 80,609,280 byte 157,440 32 8 615 7p096ata2003c25 96mb 96,731,136 byte 188,928 32 8 738 7p112ata2003c25 112mb 112,852,992 byte 220,416 32 8 861 7p128ata2003c25 128mb 128,974,848 byte 251,904 32 8 984 7p160ata2003c25 160mb 161,218,560 byte 314,880 32 16 615 notes: 1. total tracks = number of head number of cylinder. 2. total sectors/card = sectors/track number of head number of cylinder. 3. it is the logical address capacity including the area which is used for file system.
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 3 white electronic designs corporation ? (508) 366-5151 card pin assignment memory card mode i/o card mode true ide mode pin no. signal name i/o signal name i/o signal name i/o 1 gnd ? gnd ? gnd ? 2 d3 i/o d3 i/o d3 i/o 3 d4 i/o d4 i/o d4 i/o 4 d5 i/o d5 i/o d5 i/o 5 d6 i/o d6 i/o d6 i/o 6 d7 i/o d7 i/o d7 i/o 7 -ce1 i -ce1 i -ce1 i 8 a10 i a10 i a10 i 9 -oe i -oe i -atasel i 10?????? 11 a9 i a9 i a9 i 12 a8 i a8 i a8 i 13?????? 14?????? 15 -we i -we i -we i 16 rdy/-bsy o -ireq o intrq o 17 vcc ? vcc ? vcc ? 18?????? 19?????? 20?????? 21?????? 22 a7 i a7 i a7 i 23 a6 i a6 i a6 i 24 a5 i a5 i a5 i 25 a4 i a4 i a4 i 26 a3 i a3 i a3 i 27 a2 i a2 i a2 i 28 a1 i a1 i a1 i 29 a0 i a0 i a0 i 30 d0 i/o d0 i/o d0 i/o 31 d1 i/o d1 i/o d1 i/o 32 d2 i/o d2 i/o d2 i/o 33 wp o -iois16 o -iois16 o 34 gnd ? gnd ? gnd ? 35 gnd ? gnd ? gnd ?
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 4 white electronic designs corporation ? (508) 366-5151 memory card mode i/o card mode true ide mode pin no. signal name i/o signal name i/o signal name i/o 36 -cd1 o -cd1 o -cd1 o 37 d11 i/o d11 i/o d11 i/o 38 d12 i/o d12 i/o d12 i/o 39 d13 i/o d13 i/o d13 i/o 40 d14 i/o d14 i/o d14 i/o 41 d15 i/o d15 i/o d15 i/o 42 -ce2 i -ce2 i -ce2 i 43 -vs1 o -vs1 o -vs1 o 44 -iord i -iord i -iord i 45 -iowr i -iowr i -iowr i 46?????? 47?????? 48?????? 49?????? 50?????? 51 vcc ? vcc ? vcc ? 52?????? 53?????? 54?????? 55?????? 56 -csel i -csel i -csel i 57 -vs2 o -vs2 o -vs2 o 58 reset i reset i -reset i 59 -wait o -wait o iordy o 60 -inpack o -inpack o -inpack o 61 -reg i -reg i -reg i 62 bvd2 i/o -spkr i/o -dasp i/o 63 bvd1 i/o -stschg i/o -pdiag i/o 64 d8 i/o d8 i/o d8 i/o 65 d9 i/o d9 i/o d9 i/o 66 d10 i/o d10 i/o d10 i/o 67 -cd2 o -cd2 o -cd2 o 68 gnd ? gnd ? gnd ?
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 5 white electronic designs corporation ? (508) 366-5151 card pin explanation address bus (a0 to a10: input): address bus is a0 to a10. a0 is invalid in word mode. a10 is msb and a0 is lsb. in true ide mode only ha [2 : 0] are used for selecting the one of eight registers in the task file, the remaining address lines should be grounded. data bus (d0 to d15: input/output): data bus is d0 to d15. d0 is the lsb of the even byte of the word. d8 is the lsb of the odd byte of the word. card enable (-ce1, -ce2: input): -ce1 and -ce2 are low active card select signals. even addresses are controlled by -ce1 and odd addresses are by -ce2. in true ide mode -ce2 is used for select the alternate status register and the device control register while -ce1 is the chip select for the other task file registers. output enable, ata select (-oe, -astel: input): -oe is used for the control of data read in attribute area or common memory area. to enable true ide mode this input should be grounded by the host. write enable (-we: input): -we is used for the control of data write in attribute memory area or common memory area. in true ide mode this input signal is not used and should be connected to vcc. i/o read (-iord: input): -iord is used for control of read data in the task file area. this card does not respond to -iord until i/o card interface setting up. i/o write (-iowr: input): -iowr is used for control of data write in the task file area. this card does not respond to -iowr until i/o card interface setting up. ready/busy, interrupt request (rdy/-bsy, -ireq, intrq: output): in the i/o card mode, this signal is -ireq pin. the signal of low level indicates that the card is requesting software service to the host, and high level indicates that the card is not requesting. in memory card mode, the signal is rdy/-bsy pin. rdy/-bsy pin turns low level during the card internal initialization operation at v cc applied or reset applied, so the next access to the card should be after the signal turns high level. in true ide mode signal is the active high interrupt request to the host. card detection (-cd1, -cd2: output): -cd1 and -cd2 are the card detection signals. -cd1 and -cd2 are connected to ground in this card, so the host can detect if the card is inserted or not. write protect, 16 bit i/o port (wp, -iois16: output): in memory card mode, wp is held low because this card does not have a write protect switch. in the i/o card mode, -iois16 is asserted when task file registers are accessed in 16-bit mode. in true ide mode this output signal is asserted low when this device is expecting a word data transfer cycle. attribute memory area selection (-reg: input): -reg should be high level during common memory area accessing, and low level during attribute area accessing. the attribute memory area is located only in an even address, so d0 to d7 are valid and d8 to d15 are invalid in the word access mode. odd addresses are invalid in the byte access mode. in true ide mode this input signal is not used and should be connected to vcc.
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 6 white electronic designs corporation ? (508) 366-5151 battery voltage detection, digital audio output, disk active/slave present (bvd2, -spkr, -dasp: input/output): in memory card mode, bvd2 outputs the battery voltage status in the card. this card has no battery, so this output is high level constantly. in the i/o card mode, -spkr is held high because this card does not have digital audio output. in true ide mode -dasp is the disk active/slave present signal in the master/slave handshake protocol. reset (reset, -reset: input): by assertion of the reset signal, all registers of this card are cleared and the rdy/-bsy signal turns to high level. in true ide mode -reset is the active low hardware reset from the host. wait (-wait, iordy: output): this signal outputs low level for the purpose of delaying memory access cycle or i/o access cycle. in true ide mode this output signal may be used as iordy. as for this controller, this output is high impedance state constantly. input acknowledge (-inpack: output): this signal is not used in the memory card mode. this signal is asserted by this card when the card is selected and responding to an i/o read cycle at the address that is on the address bus. this signal is used for the input data buffer control. in true ide mode this output signal is not used and should be kept open at the host side. battery voltage detection, status change, pass diagnostic (bvd1, -stschg, -pdiag: input/output): in the memory card mode, bvd1 outputs the battery voltage status in the card. this card has no battery, so this output is high level constantly. in the i/o card mode, -stschg is used for changing the status of the configuration status register in the attribute area, while the card is set i/o card interface. in true ide mode, -pdiag is the pass diagnostic signal in the master/slave handshake protocol. v cc voltage sense (-vs1, -vs2: output): these signals are intended to notify the socket of the pc card's cis v cc requirement. -vs1 is held low and -vs2 is nonconnected in this card. card select (-csel: input): this signal is not used in the memory card mode and i/o card mode. this internally pulled up signal is used to configure this device as a master or a slave when configured in the true ide mode. when this pin is grounded, this device is configured as a master. when the pin is open, this device is configured as a slave.
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 7 white electronic designs corporation ? (508) 366-5151 card block diagram note: -ce1, -ce2, -oe, -we, -iord, -iowr, -reg, reset, -csel pins are pulled up in the card. -pdiag pin is schmitt trigger type input output buffer. vcc internal vcc a0 to a10 -ce1 , -ce2 wp/-iois16 -we -csel -iord reset/-reset -reg -iowr d0 to d15 -oe , -atasel rdy/-bsy/-ire q /intr q controlle r control signal -inpack bvd1/stschg/-pdiag -wait/iordy vs1 vs2 open bvd2/-spkr/-dasp -cd1 -cd2 hn29w6411a flash memory bus x?tal reset ic gnd
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 8 white electronic designs corporation ? (508) 366-5151 card function explanation register construction ? attribute region ? configuration register ? configuration option register ? configuration and status register ? pin replacement register ? socket and copy register ? cis (card i nformation s tructure) ? task file region ? data register ? error register ? feature register ? sector count register ? sector number register ? cylinder low register ? cylinder high register ? drive head register ? status register ? alternate status register ? command register ? device control register ? drive address register
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 9 white electronic designs corporation ? (508) 366-5151 host access specifications 1. attribute access specifications when the cis-rom region or the configuration register region is accessed, read and write operations are executed under the condition of -reg = "l" as follows. that region can be accessed by byte/word/odd- byte modes which are defined by the pc card standard specifications. attribute read access mode mode -reg -ce2 -ce1 a0 -oe -we d8 to d15 d0 to d7 standby mode hh high-z high-z byte access (8-bit) lhlllhhigh-zeven byte lhlhlhhigh-zinvalid word access (16-bit) l l l l h invalid even byte odd byte access (8-bit) l l h l h invalid high-z note: : l or h attribute write access mode mode -reg -ce2 -ce1 a0 -oe -we d8 to d15 d0 to d7 standby mode hh don?t care don?t care byte access (8-bit) l h l l h l don?t care even byte l h l h h l don?t care don?t care word access (16-bit) l l l h l don?t care even byte odd byte access (8-bit) l l h h l don?t care don?t care note: : l or h attribute access timing example a0 to a10 -reg -ce2/-ce1 -oe -we d0 to d15 dout read cycle din write cycle
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 10 white electronic designs corporation ? (508) 366-5151 2. task file register access specifications there are two cases of task file register mapping, one is the mapped i/o address area, the other is the mapped memory address area. each case of task file register read and write operations is executed under the condition as follows. that area can be accessed by byte/word/odd byte mode which is defined by the pc card standard specifications. (1) i/o address map task file register read access mode (1) mode -reg -ce2 -ce1 a0 -iord -iowr -oe -we d8 to d15 d0 to d7 standby mode hh high-z high-z byte access (8-bit) l hl ll hhhhigh-zeven byte l hl hl hhhhigh-z odd byte word access (16-bit) l l l l h h h odd byte even byte odd byte access (8-bit) l l h l h h h odd byte high-z note: : l or h task file register write access mode (1) mode -reg -ce2 -ce1 a0 -iord -iowr -oe -we d8 to d15 d0 to d7 standby mode hh don?t care don?t care byte access (8-bit) l h l l h l h h don?t care even byte l h l h h l h h don?t care odd byte word access (16-bit) l l l h l h h odd byte even byte odd byte access (8-bit) l l h h l h h odd byte don?t care note: : l or h task file register access timing example (1) a0 to a10 -reg -ce2/-ce1 -iord -iowr d0 to d15 dout read cycle din write cycle
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 11 white electronic designs corporation ? (508) 366-5151 (2) memory address map task file register read access mode (2) mode -reg -ce2 -ce1 a0 -oe -we -iord -iowr d8 to d15 d0 to d7 standby mode hh high-z high-z byte access (8-bit) hhl ll hhhhigh-zeven byte hhl hl hhhhigh-z odd byte word access (16-bit) h l l l h h h odd byte even byte odd byte access (8-bit) h l h l h h h odd byte high-z note: : l or h task file register write access mode (2) mode -reg -ce2 -ce1 a0 -oe -we -iord -iowr d8 to d15 d0 to d7 standby mode hh don?t care don?t care byte access (8-bit) h h l l h l h h don?t care even byte h h l h h l h h don?t care odd byte word access (16-bit) h l l h l h h odd byte even byte odd byte access (8-bit) h l h h l h h odd byte don?t care note: : l or h task file register access timing example (2) a0 to a10 -reg -ce2/-ce1 -oe -we d0 to d15 dout read cycle din write cycle
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 12 white electronic designs corporation ? (508) 366-5151 3. true ide mode the card can be configured in a true ide mode of operation. this card is configured in this mode only when the -oe input signal is asserted low by the host during the power off to power on cycle. in this true ide mode the pcmcia protocol and configuration are disabled and only i/o operations to the task file and data register are allowed. in this mode no memory or attribute registers are accessible to the host. the card permits 8 bit access if the user issues a set feature command to put the device in the 8 bit mode. true ide mode read i/o function mode -ce2 -ce1 a0 to a2 -iord -iowr d8 to d15 d0 to d7 invalid mode l l high-z high-z standby mode h h high-z high-z data register accesshl0lh odd byte even byte all status access l h 6h l h high-z status out other task file access h l 1-7h l h high-z data note: : l or h true ide mode write i/o function mode -ce2 -ce1 a0 to a2 -iord -iowr d8 to d15 d0 to d7 invalid mode l l don?t care don?t care standby mode h h don?t care don?t care data register access h l 0 h l odd byte even byte control register access l h 6h h l don?t care control in other task file access h l 1-7h h l don?t care data note: : l or h true ide mode i/o access timing example a0 to a2 -ce -iord -iowr -iois16 d0 to d15 dout read cycle write cycle din
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 13 white electronic designs corporation ? (508) 366-5151 configuration register specifications this card supports four configuration registers for the purpose of the configuration and observation of this card. 1. configuration option register (address 200h) this register is used for the configuration of the card configuration status and for the issuing the soft reset to the card. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sreset levlreq index note: initial value: 00h name r/w function sreset (host->) r/w setting this bit to "1", places the card in the reset state (card hard reset). this operation is equal to hard reset, except this bit is not cleared. then this bit is set to "0", places the card in the reset state of hard reset (this bit is set to "0" by hard reset) . card configuration status is reset and the card internal initialized operation starts when card hard reset is executed, so the next access to the card should be the same sequence as the power on sequence. levlreq (host->) r/w this bit sets to "0" when pulse mode interrupt is selected, and "1" when level mode interrupt is selected. index (host->) r/w this bit is used to select the operation mode of the card as follows. when power on, card hard reset and soft reset, this data is "000000" for the purpose of memory card interface recognition. index bit assignment index bit 5 4 3 2 1 0 card mode task file register address mapping mode 0 0 0 0 0 0 memory card 0h to fh, 400h to 7ffh memory mapped 0 0 0 0 0 1 i/o card xx0h to xxfh contiguous i/o mapped 0 0 0 0 1 0 i/o card 1f0h to 1f7h, 3f6h to 3f7h primary i/o mapped 0 0 0 0 1 1 i/o card 170h to 177h, 376h to 377h secondary i/o mapped
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 14 white electronic designs corporation ? (508) 366-5151 2. configuration and status register (address 202h) this register is used for observing the card state. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 chged sigchg iois8 0 0 pwd intr 0 note: initial value: 00h name r/w function chged (card->) r this bit indicates that the crdy/-bsy bit on the pin replacement register is set to "1". when chged bit is set to "1", the -stschg pin is held "l" at the condition of sigchg bit set to "1" and the card configured for the i/o interface. sigchg (host->) r/w this bit is set or reset by the host for enabling and disabling the status-change signal (- stschg pin). when the card is configured i/o card interface and this bit is set to "1", - stschg pin is controlled by the chged bit. if this bit is set to "0", the -stschg pin is kept "h". iois8 (host->) r/w the host sets this field to "1" when it can provide i/o cycles only with on 8 bit data bus (d7 to d0). pwd (host->) r/w when this bit is set to "1", the card enters the sleep state (power down mode). when this bit is reset to "0", the card transfers to the idle state (active mode). rrdy/-bsy bit on the pin replacement register becomes busy when this bit is changed. rrdy/- bsy will not become ready until the power state requested has been entered. this card automatically powers down when it is idle, and powers back up when it receives a command. intr (card->) r this bit indicates the internal state of the interrupt request. this bit state is available whether the i/o card interface has been configured or not. this signal remains true until the condition which caused the interrupt request has been serviced. if interrupts are disabled by the -ien bit in the device control register, this bit is a zero.
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 15 white electronic designs corporation ? (508) 366-5151 3. pin replacement register (address 204h) this register is used for providing the signal state of the -ireq signal when the card configured i/o card interface. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 crdy/-bsy 0 1 1 rrdy/-bsy 0 note: initial value: 0ch name r/w function crdy/-bsy (host->) r/w this bit is set to "1" when the rrdy/-bsy bit changes state. this bit may also be written by the host. rrdy/-bsy (host->) r/w when read, this bit indicates +ready pin states. when written, this bit is used for crdy/-bsy bit masking. 4. socket and copy register (address 206h) this register is used for identification of the card from the other cards. the host can read and write this register. this register should be set by the host before this card's configuration option register set. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 000drv#0000 note: initial value: 00h name r/w function drv# (host->) r/w this field is used for the configuration of the plural cards.
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 16 white electronic designs corporation ? (508) 366-5151 cis information cis information is defined as follows. by reading the attribute address from "0000 h", the card cis information can be confirmed. address data 7 6 5 4 3 2 1 0 description of contents cis function 000h 01h cistpl device device info tuple tuple code 002h 04h tpl_link link length is 4 bytes link to next tuple 004h dfh device type w p s device speed device type = dh: i/o device wps = 1: no wp device speed = 7: ext speed device type, wps, speed 006h 4ah ext speed mantissa speed exponent 400 ns if no wait extended speed 008h 01h 1x 2k units 2k byte of address space device size 00ah ffh list end marker end of device end marker 00ch 1ch cistpl device oc other conditions device info tuple tuple code 00eh 04h tpl_link link length is 4 bytes link to next tuple 010h 02h ext reserved v cc mwai t 3 v, wait is not used other conditions info field 012h d9h device type w p s device speed device type = dh: i/o device wps = 1: no wp device speed = 1: 250 ns device type, wps, speed 014h 01h 1x 2k units 2k byte of address space device size 016h ffh list end marker end of device end marker 018h 18h cistpl jedec c jedec id common memory tuple code 01ah 02h tpl_link link length is 2 bytes link to next tuple 01ch dfh pcmcia?s manufacturer?s jedec id code manufacturer?s id code jedec id of pc card ata 01eh 01h pcmcia jedec device code 2nd byte of jedec id 020h 20h cistpl manfid manufacturer?s id code tuple code 022h 04h tpl_link link length is 4 bytes link to next tuple 024h 07h low byte of pcmcia manufacturer?s code hitachi jedec manufacturer?s id low byte of manufacturer?s id code 026h 00h high byte of pcmcia manufacturer?s code code of 0 because other byte is jedec 1 byte manufac id high byte of manufacturer?s id code 028h 00h low byte of product code hitachi code for pc card ata low byte of product code 02ah 00h high byte of product code high byte of product code
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 17 white electronic designs corporation ? (508) 366-5151 address data 7 6 5 4 3 2 1 0 description of contents cis function 02ch 15h cistpl_ver_1 level 1 version/product info tuple code 02eh 15h tpl_link link length is 15h bytes link to next tuple 030h 04h tpplv1_major pcmcia2.0/jeida4.1 major version 032h 01h tpplv1_minor pcmcia2.0/jeida4.1 minor version 034h 48h ? h ? info string 1 036h 49h ? i ? 038h 54h ? t ? 03ah 41h ? a ? 03ch 43h ? c ? 03eh 48h ? h ? 040h 49h ? i ? 042h 00h null terminator 044h 46h ? f ? info string 2 046h 4ch ? l ? 048h 41h ? a ? 04ah 53h ? s ? 04ch 48h ? h ? 04eh 00h null terminator 050h 34h ? 4 ? vender specific strings 052h 2eh ? . ? 054h 30h ? 0 ? 056h 00h null terminator 058h ffh list end marker end of device end marker 05ah 21h cistpl funcid function id tuple tuple code 05ch 02h tpl_link link length is 2 bytes link to next tuple 05eh 04h tplfid_function = 04h disk function, may be silicon, may be removable pc card function code 060h 01h reserved r p
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 18 white electronic designs corporation ? (508) 366-5151 address data 7 6 5 4 3 2 1 0 description of contents cis function 062h 22h cistpl funce function extension tuple tuple code 064h 02h tpl_link link length is 2 bytes link to next tuple 066h 01h disk function extension tuple type disk interface type extension tuple type for disk 068h 01h disk interface type pc card ata interface interface type 06ah 22h cistpl funce function extension tuple tuple code 06ch 03h tpl_link link length is 3 bytes link to next tuple 06eh 02h disk function extension tuple type single drive extension tuple type for disk 070h 0ch reserved d u s v no v pp , silicon, single drive v = 0: no v pp required s = 1: silicon u = 1: unique serial # d = 0: single drive on card basic ata option parameters byte 1 072h 0fh r i e n p3 p2 p1 p0 p0: sleep mode supported p1: standby mode supported p2: idle mode supported p3: drive auto power control n: some config excludes 3x7 e: index bit is emulated i: twin iois16# data reg only r: reserved basic ata option parameters byte 2 074h 1ah cistpl conf configuration tuple tuple code 076h 05h tpl link link length is 5 bytes link to next tuple 078h 01h rfs rms ras rfs: reserved rms: tpcc_rmsk size - 1 = 0 ras: tpcc_radr size - 1 = 1 1 byte register mask 2 byte config base address size of fields byte tpcc_sz 07ah 03h tpcc_last entry with config index of 03h is final entry in table last entry of config registers 07ch 00h tpcc radr (lsb) configuration registers are located at 200 h in reg space location of config registers 07eh 02h tpcc radr (msb) i: configuration index c: config. and status configuration registers present mask p: pin replacement 080h 0fh reserved s p c i s: socket and copy tpcc_rmsk
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 19 white electronic designs corporation ? (508) 366-5151 address data 7 6 5 4 3 2 1 0 description of contents cis function 082h 1bh cistpl_cftable entry configuration table entry tuple tuple code 084h 08h tpl_link link length is 8 bytes link to next tuple 086h c0h i d configuration index memory mapped i/o configuration i = 1: interface byte follows d = 1: default entry configuration index = 0 configuration table index byte tpce_indx 088h c0h w r p b interface type w = 1: wait used r = 1: ready active p = 0: wp used b = 0: bvd1 and bvd2 not used if type = 0: memory interface interface description field tpce_if 08ah a1h m ms ir io t p m = 1: misc info present ms = 01: memory space info single 2-byte length ir = 0: no interrupt info present io = 0: no i/o port info present t = 0: no timing info present p = 1: v cc only info feature selection byte tpce_fs 08ch 01h r di pi ai si hv lv nv nominal voltage only follows r: reserved di: power down current info pi: peak current info ai: average current info si: static current info hv: max voltage info lv: min voltage info nv: nominal voltage info power parameters for v cc 08eh 55h x mantissa exponent nominal voltage = 5 v v cc nominal value 090h 08h length in 256 bytes pages (lsb) length of memory space is 2 kb memory space description structures (tpce ms) 092h 00h length in 256 bytes pages (msb) 094h 20h x r p r o a t x = 0: no more misc fields r: reserved p = 1: power down supported ro = 0: not read only mode a = 0: audio not supported t = 0: single drive miscellaneous features field tpce_mi
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 20 white electronic designs corporation ? (508) 366-5151 address data 7 6 5 4 3 2 1 0 description of contents cis function 096h 1bh cistpl_cftable entry configuration table entry tuple tuple code 098h 06h tpl_link link length is 6 bytes link to next tuple 09ah 00h i d configuration index memory mapped i/o configuration i = 0: no interface byte d = 0: no default entry configuration index = 0 configuration table index byte tpce_indx 09ch 01h m ms ir io t p m = 0: no misc info ms = 00: no memory space info ir = 0: no interrupt info present io = 0: no i/o port info present t = 0: no timing info present p = 1: v cc only info feature selection byte tpce_fs 09eh 21h r di pi ai si hv lv nv nominal voltage only follows r: reserved di: power down current info pi: peak current info ai: average current info si: static current info hv: max voltage info lv: min voltage info nv: nominal voltage info power parameters for v cc 0a0h b5h x mantissa exponent nominal voltage = 3.0 v v cc nominal value 0a2h 1eh x mantissa exponent +0.3 v extension byte 0a4h 4dh x mantissa exponent max average current over 10 msec is 45 ma max. average current
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 21 white electronic designs corporation ? (508) 366-5151 address data 7 6 5 4 3 2 1 0 description of contents cis function 0a6h 1bh cistpl_cftable entry configuration table entry tuple tuple code 0a8h 0ah tpl_link link length is 10 bytes link to next tuple 0aah c1h i d configuration index contiguous i/o mapped ata registers configuration i = 1: interface byte follows d = 1: default entry configuration index = 1 configuration table index byte tpce_indx 0ach 41h w r p b interface type w = 0: wait not used r = 1: ready active p = 0: wp not used b = 0: bvs1 and bvd2 not used if type = 1: i/o interface interface description field tpce_if 0aeh 99h m ms ir io t p m = 1: misc info present ms = 00: no memory space info ir = 1: interrupt info present io = 0: no i/o port info present t = 0: no timing info present p = 1: v cc only info feature selection byte tpce_fs 0b0h 01h r di pi ai si hv lv nv nominal voltage only follows r: reserved di: power down current info pi: peak current info ai: average current info si: static current info hv: max voltage info lv: min voltage info nv: nominal voltage info power parameters for v cc 0b2h 55h x mantissa exponent nominal voltage = 5 v v cc nominal value 0b4h 64h r s e io addrline s = 1: 16-bit hosts supported e = 1: 8-bit hosts supported io addrline: 4 lines decoded i/o space description field tpce_io 0b6h f0h s p l m v b i n s = 1: share logic active p = 1: pulse mode irq supported l = 1: level mode irq supported m = 1: bit mask of irqs present v = 0: no vender unique irq b = 0: no bus error irq i = 0: no io check irq n = 0: no nmi interrupt request description structure tpce_ir
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 22 white electronic designs corporation ? (508) 366-5151 address data 7 6 5 4 3 2 1 0 description of contents cis function 0b8h ffh irq 7 ir q 6 ir q 5 ir q 4 ir q 3 ir q 2 ir q 1 irq0 irq level to be routed 0 to 15 recommended mask extension byte 1 tpce_ir 0bah ffh irq 15 ir q 14 ir q 13 ir q 12 ir q 11 ir q 10 ir q 9 irq8 recommended routing to any ?normal, maskable? irq. mask extension byte 2 tpce_ir 0bch 20h x r p r o a t x = 0: no more misc fields r: reserved p = 1: power down supported ro = 0: not read only mode a = 0: audio not supported t = 0: single drive miscellaneous features field tpce_mi
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 23 white electronic designs corporation ? (508) 366-5151 address data 7 6 5 4 3 2 1 0 description of contents cis function 0beh 1bh cistpl_cftable entry configuration table entry tuple tuple code 0c0h 06h tpl_link link length is 6 bytes link to next tuple 0c2h 01h i d configuration index contiguous i/o mapped ata registers configuration i = 0: no interface byte d = 0: no default entry configuration index = 1 configuration table index byte tpce_indx 0c4h 01h m ms ir io t p m = 0: no misc info ms = 00: no memory space info ir = 0: no interrupt info present io = 0: no i/o port info present t = 0: no timing info present p = 1: v cc only info feature selection byte tpce_fs 0c6h 21h r di pi ai si hv lv nv nominal voltage only follows r: reserved di: power down current info pi: peak current info ai: average current info si: static current info hv: max voltage info lv: min voltage info nv: nominal voltage info power parameters for v cc 0c8h b5h x mantissa exponent nominal voltage = 3.0 v v cc nominal value 0cah 1eh x mantissa exponent +0.3 v extension byte 0cch 4dh x mantissa exponent max average current over 10 msec is 45 ma max. average current
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 24 white electronic designs corporation ? (508) 366-5151 address data 7 6 5 4 3 2 1 0 description of contents cis function 0ceh 1bh cistpl_cftable entry configuration table entry tuple tuple code 0d0h 0fh tpl_link link length is 15 bytes link to next tuple 0d2h c2h i d configuration index ata primary i/o mapped configuration i = 1: interface byte follows d = 1: default entry follows configuration index = 2 configuration table index byte tpce_indx 0d4h 41h w r p b interface type w = 0: wait not used r = 1: ready active p = 0: wp not used b = 0: bvs1 and bvd2 not used if type = 1: i/o interface interface description field tpce_if 0d6h 99h m ms ir io t p m = 1: misc info present ms = 00: no memory space info ir = 1: interrupt info present io = 0: no i/o port info present t = 0: no timing info present p = 1: v cc only info feature selection byte tpce_fs 0d8h 01h r di pi ai si hv lv nv nominal voltage only follows r: reserved di: power down current info pi: peak current info ai: average current info si: static current info hv: max voltage info lv: min voltage info nv: nominal voltage info power parameters for v cc 0dah 55h x mantissa exponent nominal voltage = 5 v v cc nominal value 0dch eah r s e io addrline r = 1: range follows s = 1: 16-bit hosts supported e = 1: 8-bit hosts supported io addrlines: 10 lines decoded i/o space description field tpce_io 0deh 61h ls as n range ls = 1: size of lengths is 1 byte as = 2: size of address is 2 bytes n range = 1: address range - 1 i/o range format description
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 25 white electronic designs corporation ? (508) 366-5151 address data 7 6 5 4 3 2 1 0 description of contents cis function 0e0h f0h 1st i/o base address (lsb) 1st i/o range address 0e2h 01h 1st i/o base address (msb) 0e4h 07h 1st i/o length - 1 1st i/o range length 0e6h f6h 2nd i/o base address (lsb) 2nd i/o range address 0e8h 03h 2nd i/o base address (msb) 0eah 01h 2nd i/o length - 1 2nd i/o range length 0ech eeh s p l m irq level s = 1: share logic active p = 1: pulse mode irq supported l = 1: level mode irq supported m = 0: bit mask of irqs present irq level is irq14 interrupt request description structure tpce_ir 0eeh 20h x r p r o a t x = 0: no more misc fields r: reserved p = 1: power down supported ro = 0: not read only mode a = 0: audio not supported t = 0: single drive miscellaneous features field tpce_mi
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 26 white electronic designs corporation ? (508) 366-5151 address data 7 6 5 4 3 2 1 0 description of contents cis function 0f0h 1bh cistpl_cftable entry configuration table entry tuple tuple code 0f2h 06h tpl_link link length is 6 bytes link to next tuple 0f4h 02h i d configuration index ata primary i/o mapped configuration i = 0: no interface byte d = 0: no default entry configuration index = 2 configuration table index byte tpce_indx 0f6h 01h m ms ir io t p m = 0: no misc info ms = 00: no memory space info ir = 0: no interrupt info present io = 0: no i/o port info present t = 0: no timing info present p = 1: v cc only info feature selection byte tpce_fs 0f8h 21h r di pi ai si hv lv nv nominal voltage only follows r: reserved di: power down current info pi: peak current info ai: average current info si: static current info hv: max voltage info lv: min voltage info nv: nominal voltage info power parameters for v cc 0fah b5h x mantissa exponent nominal voltage = 3.0 v v cc nominal value 0fch 1eh x mantissa exponent +0.3 v extension byte 0feh 4dh x mantissa exponent max average current over 10 msec is 45 ma max. average current
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 27 white electronic designs corporation ? (508) 366-5151 address data 7 6 5 4 3 2 1 0 description of contents cis function 100h 1bh cistpl_cftable entry configuration table entry tuple tuple code 102h 0fh tpl_link link length is 15 bytes link to next tuple 104h c3h i d configuration index ata secondary i/o mapped configuration i = 1: interface byte follows d = 1: default entry configuration index = 3 configuration table index byte tpce_indx 106h 41h w r p b interface type w = 0: wait not used r = 1: ready active p = 0: wp not used b = 0: bvs1 and bvd2 not used if type = 1: i/o interface interface description field tpce_if 108h 99h m ms ir io t p m = 1: misc info present ms = 00: no memory space info ir = 1: interrupt info present io = 0: no i/o port info present t = 0: no timing info present p = 1: v cc only info feature selection byte tpce_fs 10ah 01h r di pi ai si hv lv nv nominal voltage only follows r: reserved di: power down current info pi: peak current info ai: average current info si: static current info hv: max voltage info lv: min voltage info nv: nominal voltage info power parameters for v cc 10ch 55h x mantissa exponent nominal voltage = 5 v v cc nominal value 10eh eah r s e io addrline r = 1: range follows s = 1: 16-bit hosts supported e = 1: 8-bit hosts supported io addrlines: 10 lines decoded i/o space description field tpce_io 110h 61h ls as n range ls = 1: size of lengths is 1 byte as = 2: size of address is 2 bytes n range = 1: address range - 1 i/o range format description
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 28 white electronic designs corporation ? (508) 366-5151 address data 7 6 5 4 3 2 1 0 description of contents cis function 112h 70h 1st i/o base address (lsb) 1st i/o range address 114h 01h 1st i/o base address (msb) 116h 07h 1st i/o length - 1 1st i/o range length 118h 76h 2nd i/o base address (lsb) 2nd i/o range address 11ah 03h 2nd i/o base address (msb) 11ch 01h 2nd i/o length - 1 2nd i/o range length 11eh eeh s p l m irq level s = 1: share logic active p = 1: pulse mode irq supported l = 1: level mode irq supported m = 0: bit mask of irqs present irq level isirq14 interrupt request description structure tpce_ir 120h 20h x r p r o a t x = 0: no more misc fields r: reserved p = 1: power down supported ro = 0: not read only mode a = 0: audio not supported t = 0: single drive miscellaneous features field tpce_mi
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 29 white electronic designs corporation ? (508) 366-5151 address data 7 6 5 4 3 2 1 0 description of contents cis function 122h 1bh cistpl_cftable entry configuration table entry tuple tuple code 124h 06h tpl_link link length is 6 bytes link to next tuple 126h 03h i d configuration index ata secondary i/o mapped configuration i = 0: no interface byte d = 0: no default entry configuration index = 3 configuration table index byte tpce_indx 128h 01h m ms ir io t p m = 0: no misc info ms = 00: no memory space info ir = 0: no interrupt info present io = 0: no i/o port info present t = 0: no timing info present p = 1: v cc only info feature selection byte tpce_fs 12ah 21h r di pi ai si hv lv nv nominal voltage only follows r: reserved di: power down current info pi: peak current info ai: average current info si: static current info hv: max voltage info lv: min voltage info nv: nominal voltage info power parameters for v cc 12ch b5h x mantissa exponent nominal voltage = 3.0 v v cc nominal value 12eh 1eh x mantissa exponent +0.3 v extension byte 130h 4dh x mantissa exponent max average current over 10 msec is 45 ma max. average current 132h 14h cistpl_no_link no link control tuple tuple code 134h 00h link is 0 bytes link to next tuple 136h ffh cistpl_end end of list tuple tuple code
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 30 white electronic designs corporation ? (508) 366-5151 task file register specification these registers are used for reading and writing the storage data in this card. these registers are mapped four types by the configuration of index in the configuration option register. the decoded addresses are shown as follows. memory map (index = 0) -reg a10 a9 to a4 a3 a2 a1 a0 offset -oe = l -we = l 10 00000h data register data register 10 00011h error register feature register 10 00102h sector count registersector count register 10 00113h sector number registersector number register 10 01004h cyli nder low register cylinder low register 10 01015h cyli nder high register cylinder high register 10 01106h drive head register drive head register 10 01117h status register command register 10 10008h dup. even data registerdup. even data register 10 10019h dup. odd data registerdup. odd data register 10 1101dh dup. error register dup. feature register 10 1110eh alt. status register device control register 10 1111fh drive address register reserved 11 0 8h even data register even data register 11 1 9h odd data register odd data register
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 31 white electronic designs corporation ? (508) 366-5151 contiguous i/o map (index = 1) -reg a10 to a4 a3 a2 a1 a0 offset -iord = l -iowr = l 0 00000h data register data register 0 00011h error register feature register 0 00102h sector count registersector count register 0 00113h sector number registersector number register 0 01004h cyli nder low register cylinder low register 0 01015h cyli nder high register cylinder high register 0 01106h drive head register drive head register 0 01117h status register command register 0 10008h dup. even data registerdup. even data register 0 10019h dup. odd data registerdup. odd data register 0 1101dhdup. error register dup. feature register 0 1110eh alt. status register device control register 0 1111fh drive address register reserved primary i/o map (index = 2) -reg a10 a9 to a4 a3 a2 a1 a0 -iord = l -iowr = l 0 1fh 0000data register data register 0 1fh 0001error register feature register 0 1fh 0010sector count registersector count register 0 1fh 0011sector number registersector number register 0 1fh 0100cyli nder low register cylinder low register 0 1fh 0101cyli nder high register cylinder high register 0 1fh 0110drive head register drive head register 0 1fh 0111status register command register 0 3fh 0110alt. status register device control register 0 3fh 0111drive address register reserved
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 32 white electronic designs corporation ? (508) 366-5151 secondary i/o map (index = 3) -reg a10 a9 to a4 a3 a2 a1 a0 -iord = l -iowr = l 0 17h 0000data register data register 0 17h 0001error register feature register 0 17h 0010sector count registersector count register 0 17h 0011sector number registersector number register 0 17h 0100cyli nder low register cylinder low register 0 17h 0101cyli nder high register cylinder high register 0 17h 0110drive head register drive head register 0 17h 0111status register command register 0 37h 0110alt. status register device control register 0 37h 0111drive address register reserved true ide mode i/o map -ce2 -ce1 a2 a1 a0 -iord = l -iowr = l 10000data register data register 1 0 0 0 1 error register feature register 1 0 0 1 0 sector count register sector count register 1 0 0 1 1 sector number register sector number register 1 0 1 0 0 cylinder low register cylinder low register 1 0 1 0 1 cylinder high register cylinder high register 1 0 1 1 0 drive head register drive head register 1 0 1 1 1 status register command register 0 1 1 1 0 alt. status register device control register 0 1 1 1 1 drive address register reserved
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 33 white electronic designs corporation ? (508) 366-5151 1. data register: this register is a 16 bit register that has read/write ability, and it is used for transferring 1 sector data between the card and the host. this register can be accessed in word mode and byte mode. this register overlaps the error or feature register. bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 d0 to d15 2. error register: this register is a read only register, and it is used for analyzing the error content at the card accessing. this register is valid when the bsy bit in status register and alternate status register are set to "0" (ready). bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bbk unc ?0? idnf ?0? abrt ?0? amnf bit name function 7 bbk (bad block detected) this bit is set when a bad block is detected in requested id field. 6 unc (data ecc error) this bit is set when an uncorrectable error occurs when reading the card. 4 idnf (i d not found) the requested sector id is in error or cannot be found. 2 abrt (aborted command) this bit is set if the command has been aborted because of the card status condition. (not ready, write fault, invalid command, etc.) 0 amnf (address mark not found) this bit is set in case of a general error. 3. feature register: this register is a write only register and provides information regarding features of the drive which the host wishes to utilize. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 feature byte 4. sector count register: this register contains the numbers of sectors of data requested to be transferred on a read or write operation between the host and the card. in this card, the plural sector transfer is available across the track or cylinder. if the value of this register is zero, a count of 256 sectors is specified. in the plural sector transfer, if not successfully completed, the register contains the number of sectors which need to be transferred in order to complete the request. this register's initial value is "01h". bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sector count byte
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 34 white electronic designs corporation ? (508) 366-5151 5. sector number register: this register contains the starting sector number which is started by following a sector transfer command. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sector number byte 6. cylinder low register: this register contains the low 8 bits of the starting cylinder address which is started by following sector transfer command. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cylinder low byte 7. cylinder high register: this register contains the high 8 bits of the starting cylinder address which is started by following sector transfer command. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cylinder high byte 8. drive head register: this register is used for selecting the drive of master/slave organization and head number for the following command. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1 lba 1 drv head number bit name function 7 1 this bit is set to "1". 6 lba lba is a flag to select either cylinder / head / sector (chs) or logical block address (lba) mode. when lba=0, chs mode is selected. when lba=1, lba mode is selected. in lba mode, the logical block address is interrupted as follows: lba07-lba00 : sector number register d7-d0. lba15-lba08 : cylinder low register d7-d0. lba23-lba16 : cylinder high register d7-d0. lba27-lba24 : drive / head register bits hs3-hs0. 5 1 this bit is set to "1". 4 drv (drive select) this bit is used for selecting the master (card 0) and slave (card 1) in master/slave organization. the card is set to be card 0 or 1 by using the drv# of the socket and copy register. 3 to 0 head number this bit is used for selecting the head number for the following command. bit 3 is msb.
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 35 white electronic designs corporation ? (508) 366-5151 9. status register: this register is a read only register, and it indicates the card status of command execution. other bits are invalid when bsy bit is "1". when this register is read, -ireq is negated. when the host writes the command code to command register, bits 0, 4 and 6 are cleared and bit 7 is set. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bsy drdy dwf dsc drq corr idx err bit name function 7 bsy (busy) this bit is set when the card internal operation is executing. when this bit is set to "1", other bits in this register are invalid. 6 drdy (drive ready) if this bit and dsc bit are set to "1", the card is capable of receiving the read or write or seek requests. if this bit is set to "0", the card prohibits these requests. 5 dwf (drive write fault) this bit is set if this card indicates the write fault status. 4 dsc (drive seek complete) this bit is set when the drive seek complete. 3 drq (data request) this bit is set when the information can be transferred between the host and data register. this bit is cleared when the card receives the other command. 2 corr (corrected data this bit is set when a correctable data error has occurred and the data has been corrected. 1 idx (index) this bit is always set to "0". 0 err (error) this bit is set when the previous command has ended in some type of error. the error information is set in the other status register or error register. this bit is cleared by the next command. 10. alternate status register: this register is the same as the status register physically, so the bit assignment refers to a previous item of status register. but this register is different from the status register that -ireq is not negated when data is read. 11. command register: this register is a write only register, and it is used for writing the command at executing the drive operation. the command code written in the command register, after the parameter is written in the task file during the card, is ready state.
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 36 white electronic designs corporation ? (508) 366-5151 used parameter command command code fr sc sn cy dr hd lba check power mode e5h or 98h nnnnynn execute drive diagnostic 90h n nnnynn erase sector c0h nyyyyyy format track 50h n y n y y y y identify drive ech n nnnynn idle e3h or 97h n y n n y n n idle immediate e1h or 95h nnnnynn initialize drive parameters 91h n y n n y y n read buffer e4h n nnnynn read multiple c4h n yyyyyy read long sector 22h or 23h n n y y y y y read sector 20h or 21h n yyyyyy read verify sector 40h or 41h n yyyyyy recalibrate 1xh nnnnynn request sense 03h n nnnynn seek 7xh n n y y y y y set features efh ynnnynn set multiple mode c6h nynnynn set sleep mode e6h or 99h n nnnynn stand by e2h or 96h n nnnynn stand by immediate e0h or 94h n nnnynn translate sector 87h nyyyyyy wear level f5h nnnnyyn write buffer e8h nnnnynn write long sector 32h or 33h n n y y y y y write multiple c5h nyyyyyy write multiple w/o erase cdh nyyyyyy write sector 30h or 31h nyyyyyy write sector w/o erase 38h nyyyyyy write verify 3ch nyyyyyy note: fr: feature register sc: sector count register sn: sector number register cy: cylinder register dr: drv bit of drive head register hd: head number of drive head register lba: logical block address mode supported y: the register contains a valid parameter for this command. n: the register does not contain a valid parameter for this command.
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 37 white electronic designs corporation ? (508) 366-5151 12. device control register: this register is a write only register, and it is used for controlling the card interrupt request and issuing an ata soft reset to the card. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1srstnien0 bit name function 7 to 4 don't care 3 1 this bit is set to "1". 2 srst (software reset) this bit is set to "1" in order to force the card to perform task file reset operation. this does not change the card configuration registers as a hardware reset does. the card remains in reset until this bit is reset to "0". 1 nien (interrupt enable) this bit is used for enabling -ireq. when this bit is set to "0", -ireq is enabled. when this bit is set to "1", -ireq is disabled. 0 0 this bit is set to "0". 13. drive address register: this register is a read only register, and it is used for confirming the drive status. this register provides for compatibility with the at disk drive interface. it is recommended that this register not be mapped into the host?s i/o space because of potential conflicts on bit7. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 nwtg nhs3 nhs2 nhs1 nhs0 nds1 nds0 bit name function 7 this bit is unknown 6 nwtg (writing gate) this bit is unknown 5 to 2 nhs3-0 (head select3-0) these bits are the negative value of head select bits (bit 3 to 0) in thedrive/head register. 1 nds1 (idrive select1) this bit is unknown 0 nds0 (idrive select0) this bit is unknown
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 38 white electronic designs corporation ? (508) 366-5151 ata command specifications this table summarizes the ata command set with the paragraphs. the following shows the support commands and command codes which are written in the command registers.
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 39 white electronic designs corporation ? (508) 366-5151 ata command set no. command set code fr sc sn cy dr hd lba 1 check power mode e5h or 98h ????y ?? 2 execute drive diagnostic 90h ? ???y ?? 3 erase sector(s) c0h ?yyyyyy 4 format track 50h ? y ? y y y y 5 identify drive ech ? ???y ?? 6 idle e3h or 97h ? y ? ? y ? ? 7 idle immediate e1h or 95h ????y ?? 8 initialize drive parameters 91h ? y ? ? y y ? 9 read buffer e4h ? ???y ?? 10 read multiple c4h ? yyyyyy 11 read long sector 22h, 23h ? ? y y y y y 12 read sector (s) 20h, 21h ? yyyyyy 13 read verify sector (s) 40h, 41h ? yyyyyy 14recalibrate 1xh ????y ?? 15 request sense 03h ? ???y ?? 16 seek 7xh ? ? y y y y y 17set features efh y ???y ?? 18set multiple mode c6h ?y ??y ?? 19 set sleep mode e6h or 99h ? ???y ?? 20 stand by e2h or 96h ? ???y ?? 21 stand by immediate e0h or 94h ? ???y ?? 22translate sector 87h ?yyyyyy 23wear level f5h ????y y ? 24write buffer e8h ????y ?? 25 write long sector 32h or 33h ? ? y y y y y 26write multiple c5h ?yyyyyy 27write multiple w/o erase cdh ?yyyyyy 28write sector 30h or 31h ?yyyyyy 29write sector(s) w/o erase 38h ?yyyyyy 30write verify 3ch ?yyyyyy note: fr: feature register sc: sector count register (00h to ffh) sn: sector number register (01h to 20h) cy: cylinder low/high register (to) dr: drive bit of drive/head register hd: head no.(0 to 3) of drive/head register nh: no. of heads y: set up ?: not set up
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 40 white electronic designs corporation ? (508) 366-5151 1. check power mode (code: e5h or 98h): this command checks the power mode. 2. execute drive diagnostic (code: 90h): this command performs the internal diagnostic tests implemented by the card. 3. erase sector(s) (code: c0h): this command is used to pre-erase and condition data sectors in advance of a write without erase or write multiple without erase command. 4. format track (code: 50h): this command writes the desired head and cylinder of the selected drive but the selected sector data is not exchanged. this card accepts a sector buffer of data from the host to follow the command with same protocol as the write sector command. 5. identify drive (code: ech): this command enables the host to receive parameter information from the card. identify drive information word address default value total bytes data field type information 0 848ah 2 general configuration bit-significant information 1 xxxx 2 default number of cylinders 2 0000h 2 reserved 3 00xxh 2 default number of heads 4 0000h 2 number of unformatted bytes per track 5 xxxx 2 number of unformatted bytes per sector 6 xxxx 2 default number of sectors per track 7 to 8 xxxx 4 number of sectors per card (word7 = msw, word8 = lsw) 9 0000h 2 reserved 10 to 19 xxxx 20 reserved 20 0002h 2 buffer type (dual ported) 21 0002h 2 buffer size in 512 byte increments 22 0004h 2 # of ecc bytes passed on read/write long commands 23 to 46 xxxx 48 firmware revision in ascii etc. 47 0001h 2 maximum of 1 sector on read/write multiple command 48 0000h 2 double word not supported 49 0200h 2 capabilities: dma not supported (bit 8), lba supported (bit9) 50 0000h 2 reserved 51 0100h 2 pio data transfer cycle timing mode 1 52 0000h 2 dma data transfer cycle timing mode not supported 53 to 58 xxxx 12 reserved 59 010xh 2 multiple sector setting is valid 60 to 61 xxxx 4 total number of sectors addressable in lba mode 62 to 255 0000h 388 reserved
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 41 white electronic designs corporation ? (508) 366-5151 6. idle (code: e3h or 97h): this command causes the card to set bsy, enter the idle mode, clear bsy and generate an interrupt. if the sector count is non-zero, the automatic power down mode is enabled. if the sector count is zero, the automatic power down mode is disabled. 7. idle immediate (code: e1h or 95h): this command causes the card to set bsy, enter the idle (read) mode, clear bsy and generate an interrupt. 8. initialize drive parameters (code: 91h): this command enables the host to set the number of sectors per track and the number of heads per cylinder. 9. read buffer (code: e4h): this command enables the host to read the current contents of the card's sector buffer. 10. read multiple (code: c4h): this command performs similarly to the read sectors command. interrupts are not generated on each sector, but on the transfer of a block which contains the number of sectors defined by a set multiple command. 11. read long sector (code: 22h or 23h): this command performs similarly to the read sector(s) command except that it returns 516 bytes of data instead of 512 bytes. 12. read sector(s) (code: 20h, 21h): this command reads from 1 to 256 sectors as specified in the sector count register. a sector count of 0 requests 256 sectors. the transfer begins at the sector specified in the sector number register. 13. read verify sector (code: 40h or 41h): this command is identical to the read sectors command, except that drq is never set and no data is transferred to the host . 14. recalibrate (code: 1xh): this command is effectively a nop command to the card and is provided for compatibility purposes. 15. request sense (code: 03h): this command requests an extended error code after a command ends with an error. 16. seek (code: 7xh): this command is effectively a nop command to the card although it does perform a range check. 17. set features (code: efh): this command is used by the host to establish or select certain features. feature operation 01h enable 8-bit data transfers. 55h disable read look ahead. 66h disable power on reset (por) establishment of defaults at soft reset. 81h enable 8-bit data transfers. bbh 4 bytes of data apply on read/write long commands. cch enable power on reset (por) establishment of defaults at soft reset. 18. set multiple mode (code: c6h): this command enables the card to perform read and write multiple operations and establishes the block count for these commands. 19. set sleep mode (code: e6h or 99h): this command causes the card to set bsy, enter the sleep mode, clear bsy and generate an interrupt. 20. stand by (code: e2h or 96h): this command causes the card to set bsy, enter the sleep mode (which corresponds to the ata "standby" mode), clear bsy and return the interrupt immediately.
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 42 white electronic designs corporation ? (508) 366-5151 21. stand by immediate (code: e0h or 94h): this command causes the card to set bsy, enter the sleep mode(which corresponds to the ata "standby" mode), clear bsy and return the interrupt immediately. 22. translate sector (code: 87h): this command allows the host a method of determining the exact number of times a user sector has been erased and programmed. 23. wear level (code: f5h): this command is effectively a nop command and is only implemented for backward compatibility. 24. write buffer (code: e8h): this command enables the host to overwrite contents of the card's sector buffer with any data pattern desired. 25. write long sector (code: 32h or 33h): this command is provided for compatibility purposes and is similar to the write sector(s) command except that it writes 516 bytes instead of 512 bytes. 26. write multiple (code: c5h): this command is similar to the write sectors command. interrupts are not presented on each sector, but on the transfer of a block which contains the number of sectors defined by set multiple command. 27. write multiple without erase (code: cdh): this command is similar to the write multiple command with the exception that an implied erase before write operation is not performed. 28. write sector(s) (code: 30h or 31h): this command writes from 1 to 256 sectors as specified in the sector count register. a sector count of zero requests 256 sectors. the transfer begins at the sector specified in the sector number register. 29. write sector(s) without erase (code: 38h): this command is similar to the write sector(s) command with the exception that an implied erase before write operation is not performed. 30. write verify (code: 3ch): this command is similar to the write sector(s) command, except each sector is verified immediately after being written.
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 43 white electronic designs corporation ? (508) 366-5151 sector transfer protocol 1. sector read: 1 sector read procedure after the card configured i/o interface is shown as follows. (1) set the logical sector number (2) (4) burst data transfer (3) (5) set the c y linder low / hi g h re g iste r set the head no. of drive head register set the sector number register set ?01h? in sector count register set ?20h? in command register read 256 times the data ( 512 b y tes ) read status re g iste r wait the command input start read status register 58h 50h i/o access index = 1 ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) a 0 to a10 -ce1 -ce2 -iowr -iord d0 to d15 -ireq 01h20h 80h 58h ( transfer data ) 80h 50h 4h 5h 6h 3h 2h 7h 7h 7h 0h 0h 7h 7h
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 44 white electronic designs corporation ? (508) 366-5151 2. sector write: 1 sector write procedure after the card configured i/o interface is shown as follows. (1) set the logical sector number (2) (4) burst data transfer (3) (5) set the cylinder low / high register set the head no. of drive head re g iste r set the sector number re g iste r set ?01h? in sector count register set ?30h? in command register write 256 times the data ( 512 b y tes ) read status register wait the command input start read status register 58h 50h i/o access index = 1 ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) a 0 to a10 -ce1 -ce2 -iowr -iord d0 to d15 -ireq 01h30h 80h 58h ( data transfer ) 80h 50h 4h 5h 6h 3h 2h 7h 7h 7h 0h 0h 7h 7h
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 45 white electronic designs corporation ? (508) 366-5151 absolute maximum ratings parameter symbol value unit note all input/output voltages vin, vout ?0.3 to v cc + 0.3 v 1 v cc voltage v cc ?0.3 to +6.5 v operating temperature range commercial industrial topr 0 to +60 -40 to +85 c storage temperature range commercial industrial tstg ?20 to +65 -40 to +85 c note: 1. vin, vout min = ?2.0 v for pulse width 20 ns. recommended dc operating conditions voltage reference to gnd, commercial ta =0 to 65c , industrial ta=-40 to +85c parameter symbol min typ max unit note operating temperature commercial industrial ta 0 -40 25 +60 +85 c v cc voltage v cc 4.5 5.0 5.5 v 3.15 3.3 3.45 v capacitance (ta = 25 c, f = 1mhz) parameter symbol min typ max unit test conditions input capacitance cin ? ? 35 pf vin = 0 v output capacitance cout ? ? 35 pf vout = 0 v system performance item performance start up times (reset to ready) 100 ms (max) start up times (sleep to idle) 2 ms (max) data transfer rate to/from host 8 mb/s burst controller overhead (command to drq) 2 ms (max) data transfer cycle end to ready (sector write) 1.2 ms (typ)
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 46 white electronic designs corporation ? (508) 366-5151 dc characteristics-1 (commercial ta = 0 to +60 c, v cc = 5.0 v 10%) (industrial ta = -40 to +85 c, v cc = 5.0 v 10%) parameter symbol min typ max unit test conditions note input leakage current i li ? ? 1 a vin = gnd to v cc 1 input voltage (cmos) v il ??0.8v v ih 4.0??v input voltage (schmitt trigger) v il ?2.0?v v ih ?2.8?v output voltage v ol ??0.4vi ol = 8 ma v oh v cc ? 0.8 ? ? v i oh = ?8 ma note: 1. except pulled up input pin. dc characteristics-2 (ta = 0 to +60 c, v cc = 3.3 v 5%) (ta = -40 to +85 c, v cc = 3.3 v 5%) parameter symbol min typ max unit test conditions note input leakage current i li ? ? 1 a vin = gnd to v cc 1 input voltage (cmos) v il ??0.6v v ih 2.4??v input voltage (schmitt trigger) v il ?1.0?v v ih ?1.8?v output voltage v ol ??0.4vi ol = 8 ma v oh v cc ? 0.8 ? ? v i oh = ?8 ma note: 1. except pulled up input pin.
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 47 white electronic designs corporation ? (508) 366-5151 dc characteristics-3 (ta = 0 to +60 c, v cc = 5.0 v 10%) (industrial ta = -40 to +85 c, v cc = 5.0 v 10%) 8mb/16mb 32mb/48mb 64mb/80mb 96mb 112mb/128 mb/150mb parameter symbol typ max typ max typ max unit test conditions sleep/standby current i sp1 0.5 1.0 0.7 1.5 1.0 2.0 ma cmos level (control signal = v cc ? 0.2 v in memory card mode and i/o card mode) sector read current i ccr (dc) 40 75 40 75 40 75 ma i ccr (peak) 80 120 80 120 80 120 cmos level (control signal = v cc ? 0.2 v) during sector read transfer sector write current i ccw (dc) 45 75 45 75 45 75 ma i ccw (peak) 80 120 80 120 80 120 cmos level (control signal = v cc ? 0.2 v) during sector write transfer dc characteristics-4 (ta = 0 to +60 c, v cc = 3.3 v 5%) (ta = -40 to +85 c, v cc = 3.3 v 5%) 8mb/16mb 32mb/48mb 64mb/80mb 96mb 112mb/128 mb/160mb parameter symbol typ max typ max typ max unit test conditions sleep/standby current i sp1 0.3 0.6 0.4 0.8 0.5 1.0 ma cmos level (control signal = v cc ? 0.2 v in memory card mode and i/o card mode) sector read current i ccr (dc) 25 50 25 50 25 50 ma i ccr (peak)5080 5080 5080 cmos level (control signal = v cc ? 0.2 v) during sector read transfer sector write current i ccw (dc) 25 50 25 50 25 50 ma i ccw (peak) 50 80 50 80 50 80 cmos level (control signal = v cc ? 0.2 v) during sector write transfer
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 48 white electronic designs corporation ? (508) 366-5151 dc current waveform (example of sector read or write: v cc = 5 v, ta = 25 c) power on operation (reference only) curren t dc power o n time
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 49 white electronic designs corporation ? (508) 366-5151 sector read sector write command write complete of sector read iccr ( dc ) time iccr(peak) current command write complete of sector write iccw(dc) time iccw(peak) current
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 50 white electronic designs corporation ? (508) 366-5151 ac characteristics (commercial ta=0 to +60 c, v cc = 5 v 10%, v cc = 3.3 v 5%) ( industrial ta= -40 to +85 c, v cc = 5.0 v 10%, v cc = 3.3 v 5% ) attribute memory read ac characteristics 250 ns parameter symbol min typ max unit read cycle time tcr 250 ? ? ns address access time ta(a) ? ? 250 ns -ce access time ta(ce) ? ? 250 ns -oe access time ta(oe) ? ? 125 ns output disable time (-ce) tdis(ce) ? ? 100 ns output disable time (-oe) tdis(oe) ? ? 100 ns output enable time (-ce) ten(ce) 5 ? ? ns output enable time (-oe) ten(oe) 5 ? ? ns data valid time (a) tv(a) 0 ? ? ns address setup time tsu(a) 30 ? ? ns address hold time th(a) 20 ? ? ns -ce setup time t su(ce) 0 ? ? ns -ce hold time t h(ce) 20 ? ? ns attribute memory read timing
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 51 white electronic designs corporation ? (508) 366-5151 attribute memory write ac characteristics 250 ns parameter symbol min typ max unit write cycle time tcw 250 ? ? ns write pulse time tw(we) 150 ? ? ns address setup time tsu(a) 30 ? ? ns address setup time (-we) tsu(a-weh) 180 ? ? ns -ce setup time (-we) tsu(ce-weh) 180 ? ? ns data setup time (-we) tsu(d-weh) 80 ? ? ns data hold time th(d) 30 ? ? ns write recover time trec(we) 30 ? ? ns output disable time (-we) tdis(we) ? ? 100 ns output disable time (-oe) tdis(oe) ? ? 100 ns output enable time (-we) ten(we) 5 ? ? ns output enable time (-oe) ten(oe) 5 ? ? ns output enable setup time (-we) tsu(oe-we) 10 ? ? ns output enable hold time (-we) th(oe-we) 10 ? ? ns -ce setup time t su(ce) 0 ? ? ns -ce hold time t h(ce) 20 ? ? ns attribute memory write timing
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 52 white electronic designs corporation ? (508) 366-5151 i/o access read ac characteristics parameter symbol min typ max unit data delay after -iord td(iord) ? ? 100 ns data hold following -iord th(iord) 0 ? ? ns -iord pulse width tw(iord) 165 ? ? ns address setup before -iord tsua(iord) 70 ? ? ns address hold following -iord tha(iord) 20 ? ? ns -ce setup before -iord tsuce(iord) 5 ? ? ns -ce hold following -iord thce(iord) 20 ? ? ns -reg setup before -iord tsureg(iord) 5 ? ? ns -reg hold following -iord threg(iord) 0 ? ? ns -inpack delay falling from -iord tdfinpcak(iord) 0 ? 45 ns -inpack delay rising from -iord tdrinpack(iord) ? ? 45 ns -iois16 delay falling from address tdfiois16(iord) ? ? 35 ns -iois16 delay rising from address tdriois16(iord) ? ? 35 ns i/o access read timing
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 53 white electronic designs corporation ? (508) 366-5151 i/o access write ac characteristics parameter symbol min typ max unit data setup before -iowr tsu(iowr) 60 ? ? ns data hold following -iowr th(iowr) 30 ? ? ns -iowr pulse width tw(iowr) 165 ? ? ns address setup before -iowr tsua(iowr) 70 ? ? ns address hold following -iowr tha(iowr) 20 ? ? ns -ce setup before -iowr tsuce(iowr) 5 ? ? ns -ce hold following -iowr thce(iowr) 20 ? ? ns -reg setup before -iowr tsureg(iowr) 5 ? ? ns -reg hold following -iowr threg(iowr) 0 ? ? ns -iois16 delay falling from address tdfiois16(adr) ? ? 35 ns -iois16 delay rising from address tdriois16(adr) ? ? 35 ns i/o access write timing
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 54 white electronic designs corporation ? (508) 366-5151 common memory access read ac characteristics parameter symbol min typ max unit -oe access time ta(oe) ? ? 125 ns output disable time (-oe) tdis(oe) ? ? 100 ns address setup time tsu(a) 30 ? ? ns address hold time th(a) 20 ? ? ns -ce setup time tsu(ce) 0 ? ? ns -ce hold time th(ce) 20 ? ? ns common access read timing
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 55 white electronic designs corporation ? (508) 366-5151 common memory access write ac characteristics parameter symbol min typ max unit data setup time (-we) tsu(d-weh) 80 ? ? ns data hold time th(d) 30 ? ? ns write pulse time tw(we) 150 ? ? ns address setup time tsu(a) 30 ? ? ns -ce setup time tsu(ce) 0 ? ? ns write recover time trec(we) 30 ? ? ns -ce hold following -we th(ce) 20 ? ? ns common access write timing
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 56 white electronic designs corporation ? (508) 366-5151 true ide mode access read ac characteristics parameter symbol min typ max unit data delay after iord td(iord) ? ? 100 ns data hold follwing iord th(iord) 0 ? ? ns iord width time tw(iord) 165 ? ? ns address setup before iord tsua(iord) 70 ? ? ns address hold following iord tha(iord) 20 ? ? ns ce setup before iord tsuce(iord) 5 ? ? ns ce hold following iord thce(iord) 20 ? ? ns iois16 delay falling from address tdfiois16(adr) ? ? 35 ns iois16 delay rising from address tdfiois16(adr) ? ? 35 ns true ide mode access read timing -i/owr: high fix, -oe: low fix, -we: high fix valid output tdriois(adr) -iois16 d0 to d15 -ce2/-ce1 -iord a0 to a2 td(iord) tw(iord) tsua(iord) tsuce(iord) thce(iord) tha(iord) tdriois(adr) th(iois)
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 57 white electronic designs corporation ? (508) 366-5151 true ide mode access write ac characteristics parameter symbol min typ max unit data setup before iowr tsu(iowr) 60 ? ? ns data hold following iowr th(iowr) 30 ? ? ns iord width time tw(iowr) 165 ? ? ns address setup before iowr tsua(iowr) 70 ? ? ns address hold following iowr tha(iowr) 20 ? ? ns ce setup before iowr tsuce(iowr) 5 ? ? ns ce hold following iowr thce(iowr) 20 ? ? ns iois16 delay falling from address tdfiois16(adr) ? ? 35 ns iois16 delay rising from address tdfiois16(adr) ? ? 35 ns true ide mode access write timing -i/ord: high fix, -oe: low fix, -we: high valid output tdriois(adr) -iois16 d0 to d15 -ce2/-ce1 -iowr a0 to a2 tsu(iowr tw(iowr) tsua(iowr) tsuce(iord) thce(iord) tha(iowr) tdriois(adr) th(iowr)
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 58 white electronic designs corporation ? (508) 366-5151 reset characteristics (only memory card mode or i/o card mode) hard reset characteristics parameter symbol min typ max unit test conditions reset setup time tsu(reset) 100 ? ? ms -ce recover time trec(vcc) 1 ? ? s vcc rising up time tpr 0.1 ? 100 ms vcc falling down time tpf 3 ? 300 ms reset pulse width tw(reset) 10 ? ? s th(hi-zreset) 1 ? ? ms ts(hi-zreset) 0 ? ? ms hard reset timing
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 59 white electronic designs corporation ? (508) 366-5151 power on reset characteristics all card status are reset automatically when v cc voltage goes over about 2.3 v. parameter symbol min typ max unit test conditions -ce setup time tsu(vcc) 100 ? ? ms vcc rising up time tpr 0.1 ? 100 ms power on reset timing attention for card use ? in the reset or power off, all register information is cleared. ? all card status are cleared automatically when vcc voltage turns below about 2.5v. ? after the card hard reset, soft reset, or power on reset, the card cannot access during +ready pin is "low" level. ? please notice that the card insertion/removal should be executed after card internal operations are completed (status register bit 7 turns from "1" to "0"). ? unused pins of data bus (d0 to d15) signals should not be opened. ? v cc should not be supplied to the card until it is completely inserted. after confirmation that the ?cd1 and ?cd2 pins are inserted v cc can be supplied to the card. only use drives that will wait until the card is completely inserted to supply v cc . ? -oe must be kept at the v cc level during power on reset in memory card mode. ?oe must be kept constantly at the gnd level in true ide mode. t su ( vcc ) t pr vcc -ce1, -ce2
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 60 white electronic designs corporation ? (508) 366-5151 physical outline 54.0mm 0.10 10.0mm min 1.6mm 0.05 1.0mm 0.05 1.0mm 0.05 3.3mm t1 (0.130?) t1=0.10mm interconnect area interconnect area 10.0mm min 3.0mm min 85.6mm 0.20 substrate area min 1.6mm 0.05 10.0mm 5.0mm t1 1.0mm 85.6mm 0.20 3.0mm 54.0mm 0.10 1.0mm substrate area interconnect area
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 61 white electronic designs corporation ? (508) 366-5151 product marking wed7p016ata2000c15 c995 9915 note: some products are currently marked with our pre-merger company name/acronym (edi). during our transition period some products will also be marked with our new company name/acronym (wed). startin g october 2000 all pcmcia products will be marked only with wed prefix. edi company name lot code / trace number date code part number
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 62 white electronic designs corporation ? (508) 366-5151 part numbering 7 p 016ata2000c 15 card capacity 016 16mb packaging option 00 standard, type 1 pc car d pstandard pcmcia r ruggedized pcmcia card family and version - see card family and version info. for details (next page) t emperature range c commercial 0c to + 70c i industrial -40c to +85c card access time 15 150ns 25 250ns card technology 7 flash 8 sram
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 63 white electronic designs corporation ? (508) 366-5151 ordering information 7p xxx ata yy ss t zz where xxx (unformatted capacity): 008 8mb 016 16mb 032 32mb 048 48mb 064 64mb 080 80mb 96 96mb 112 112mb 128 128mb 160 160mb yy: 20 standard, 3v/5v: (controller type = hn) ss: 00 wedc flash ata logo type i 01 blank housing type i 02 blank housing type i recessed 03 wedc flash ata logo type ii 04 blank housing type ii 05 blank housing type ii recessed t: c commercial temperature range i industrial temperature range zz: 25 250ns
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 64 white electronic designs corporation ? (508) 366-5151 revision record rev. date contents of modification drawn by approved by 0.0 june 16, 1998 initial issue w. brys 0.1 january 25, 1999 card line up table card pin explanation changes for wait and inpack new block diag and note cis changes: reformat cis and changes in addresses: 004h, 010h, 012h, 050h, 05ah, 070h, 072h, 07ah, 080h, 088h, ata command specifications - 5. identify drive information (table) (page 40) change of data field type information: word address 1 change of total bytes: word address 7 to 8 change of total default value: word address 51 dc characteristics-3 (5 v) change of test conditions: cmos level between to cmos level during i sp1 typ: 0.5 ma to 0.5/0.7/1.0 ma i sp1 max: tbd to 1.0/1.5/2.0 ma i ccr (dc) typ: 50 ma to 40/40/40 ma i ccr , i ccw (dc) max: tbd to 75/75/75 ma i ccw (dc) typ: 0.5 ma to 45/45/45 ma i ccr , i ccw (peak) typ: 100 ma to 80 ma i ccr , i ccw (peak) max: tbd to 120 ma dc characteristics-4 (3.3 v) change of test conditions: cmos level between to cmos level during i sp1 typ: 0.3 ma to 0.3/0.4/0.5 ma i sp1 max: tbd to 0.6/0.8/1.0 ma i ccr , i ccw (dc) typ: 30 ma to 25/25/25 ma i ccr , i ccw (dc) max: tbd to 50/50/50 ma i ccr , i ccw (peak) typ: 60 ma to 50/50/50 ma i ccr , i ccw (peak) max: tbd to 80/80/80 ma power on reset characteristics tsu(reset), tsu(vcc) min: 250 ms to 100 ms w. brys w. wrotek 0.2 april 9, 1999 page 1: add ?industrial temp range? w. brys w. wrotek 0.3 may 14, 1999 add industrial temp range to the specification company name change w. brys w. wrotek 0.4 august 27, 1999 page 1: added the 112mb and 128mb capacities and their part numbers to the list of ata20 series cards. in the features section, type i housing was added to the specifications to reflect the choice between type i and type ii housing. in the features section, the part number for the hitachi memory component was changed from hn29w6411 to hn29w6411a, to reflect the new memory component used for these cards. in the features section, the data write endurance was changed from 100,000 cycles to 300,000. this change is resulting from the change in memory m. garrett w. brys
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 65 white electronic designs corporation ? (508) 366-5151 components. page 2: two rows were added to the card line up to show the values for the new 112mb and 128mb capacities. page 17: in the cis information, at address 050h, the value was changed from 033h from 034h (from 3 to 4 in decimal), to reflect the new revision of the card. page 43: ?wait the command input? was added to the bottom bubble of the sector read flow chart. this was previously missing from the chart. the sector read timing diagram was converted from a picture to a microsoft word object to decrease file size. page 44: the sector write timing diagram was converted from a picture to a microsoft word object to decrease file size. page 45: the data transfer cycle end to ready (sector write) value was changed from 2ms to 1.2ms (typ.). this change is resulting from the change in memory components. page 47: the capacity headings on both the dc characteristics-3 and dc characteristics-4 tables changed from 8mb/15mb/30mb/45mb, 60mb/75mb/90mb, and 150mb to 8mb/16mb/32mb/48mb, 64mb/80mb/96mb, and 112mb/128mb/160mb. this change reflects the addition of the 112mb and 128mb capacities, and the change of designations for the other cards, which were labeled with the old capacity values, though the capacities were actually what they are labeled now. the test conditions for the sleep/standby current, for both the dc charcteristics-3 and dc characteristics-4 tables have the phrase ?in memory card mode and i/o card mode? appended to them. the sector write current values for each capacity column in the dc characteristics-3 table were changed from 50/100,tbd/tbd to 45/80,75/120 in ma (dc/peak for typ and max respectively). page 48: new waveform (ms word object) added for power on operation, in the dc current waveform section. page 49: the old waveforms (ms word objects) for sector read current and sector write current, in the dc current waveform section, were replaced with updated waveforms for each.
7pxxxata20xxc25 june 2000 rev. 5 ? eco #12935 66 white electronic designs corporation ? (508) 366-5151 page 57: in the hard reset characteristics table, the minimum value for reset setup time changed from 250ms to 100ms. page 59: under ?attention for card use?, the information following the final two bullets was added. page 60: the mechanical drawing for a type i housing was added to the physical outline section, since the cards are now available in a type i housing. page 61: under ordering information, the digits needed to order the new 112mb and 128mb capacity cards were added. under ordering information, the digits needed to order cards in a type i housing were added, since this option was not available before. 0.5 june 2, 2000 added page 61 & 62 m. garrett file: f:\marcom\data sheets-new\data sheets ? commercial\ata20 dsht rev 5.doc

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